*** Use the following information at your own risk.   I offer no guarantee that this information is without defects or design flaws.
It will have the 65816 microprocessor, running at 7.159 MHz. It can directly address the 512K of system RAM. During /RESET, the CPLD will hold the /RES line low while it copies the EEPROM to RAM from $08000 to $0FFFF. Once done, it releases the /RES and the 65816 starts executing instructions from RAM. The EEPROM is placed in low-power standby while the MPU is running.
The video system uses the transparent DMA method. During the low phase of PHI2, the CPLD accesses RAM and outputs pixel data to the video system. During the high phase of PHI2, the CPLD lets the MPU access RAM.
I was inspired to use this video display hardware when I found this General Purpose Display Controller on the Internet.
The Video output is 320x200 pixels, using 8 bits per pixel (256 colors). This uses 64000 bytes for an entire screen. The CPLD holds a 3 bit video display register that selects which 64k byte block of RAM to display. At start-up, the Video display register is set to 001 ($10000-1F9FF). The data from $1FA00 to $1FDE7 is used for text data (40 characters x 25 lines). The default text font is 8x8 pixels per character. Address $1FDE8 to $1FFF is not used by the video system and can be used for general storage. To change the video display register, you can write the block number ($00 to $07) to address $00300. Reading that address will give you the current block in bits 0-2. bit 7 contains the vertical sync flag; 1 = vertical sync, 0 = no vertical sync. bits 3-6 are not used. Changes to the Video display register will take affect during the next vertical refresh, so there should not be any flicker. There is also a Video Interupt pin that can be connected to the NMI interrupt or to other logic that is active low during the 3 vertical sync lines.
The pixel data is formatted as BBGGGRRR (Bits 0-2 are Red, 3-5 are Green, and 6-7 are Blue). A resistor network forms a voltage divider to convert the bits to analog votages from 0 to 0.7V for each color. These are fed into the AD724 to generate the color display.
The prototype core is complete and is running. The ExpressPCB files are in the Downloads section.
Here is the Core Schematic:
This is the V1.0 Core:
The wire wrapped on J1 is pulling /IRQ high as I didn't have room for a pull-up on the board. The final board will have ample room for all parts.
This is a self image - the top picture was imported to the SBC-3 core and this is a picture of my TV.
Here is the top layer with parts placement:
As you can see, it barely fit on the ExpressPCB miniboard (2.5" x 3.8").
Here is the bottom layer: