Here is the actual parts list: (See SBC-1 Pictures for placement guide)
IC1 - 40 pin DIP - 65C02 microprocessor
IC2 - 28 pin DIP - 62256 static RAM (or pin compatible replacement)
IC3 - 28 pin DIP - 28256 EEPROM (or pin compatible replacement)
IC4 - 40 pin DIP - 6522 or 6526 (or pin compatible IO chip)
IC5 - 14 pin DIP - 74LS30 8-IN NAND gate
IC5 - 14 pin DIP - 74LS00 quad 2-IN NAND gate
IC6 - 14 pin DIP - 74LS00 quad 2-IN NAND gate
OSC1 - 4 pin DIP - 1MHZ TTL Oscillator in full size (14 pin footprint)
or half size (8 pin footprint) can
C1 - 220uF Electrolytic Capacitor (power filter)
C2 - 100uF Electrolytic Capacitor (power-on reset)
C3 - 0.1uF ceramic capacitor ( power filter)
C4 - 0.1uF ceramic capacitor (bypass for 74LS chips)
C5 - 0.1uF ceramic capacitor (bypass for EEPROM)
C6 - 0.1uF ceramic capacitor (bypass for RAM)
C7 - 0.1uF ceramic capacitor (bypass for 65C02)
C8 - 0.1uF ceramic capacitor (bypass for 6522)
RP-1 - 10 pin SIP - 22k bussed resistor pack (9 resistors with one side common)
RP-2 - 6 pin SIP - 10k bussed resistor pack (5 resistors with one side common)
J1 - 2 pin SIP - EEPROM write enable jumper
J2 - 6 pin SIP - 6522/6526 configuration jumpers (see below for info)
SW-1 - 2 pins (0.175" spacing) - SPST reset switch
PWR-IN - 2 pins (0.1" spacing) for regulated +5vdc input
CON-1 - 26 pin header ( 2x13, 0.1" centers) for 6522 I/O (see below for pinout)
CON-2 - 4 pin header (1x4 0.1" spacing) +5,CA1,CA2,gnd connections (serial data and clock from 6526)
CON-3 - 4 pin header (1x4 0.1" spacing) +5,CB1,CB2,gnd connections (serial data and clock from 6522)
I will briefly describe each of the added pads and their possible use:
P1 - extra +5vdc tap
P2 - extra reset tap or extra pullup if trace is cut (see reset below)
P3 - spare resistor tap (use if a pullup is needed somewhere)
P4 - extra reset tap
P5 - RDY from 65c02 tap
P6 - +5vdc tap (could be used with 6522 device select)
P7 - Memory Write strobe tap
P8 - Memory Read strobe tap
P9 - A3 address line tap (used for additional IO decoding)
P10 - A2 address line tap (used for additional IO decoding)
P11 - A1 address line tap (used for additional IO decoding)
P12 - A0 address line tap (used for additional IO decoding)
P13 - A4 address line tap (used for additional IO decoding)
P14 - A5 address line tap (used for additional IO decoding)
P15 - A6 address line tap (used for additional IO decoding)
P16 - A7 address line tap (used for additional IO decoding)
P17 - extra ground tap
P18 - 1st spare NAND gate input (wired an an inverter)
P19 - extra ground tap
P20 - 2nd spare NAND gate input (wired an an inverter)
P21 - output of a 2nd spare NAND gate (inverter output)
P22 - output of a 3rd spare NAND gate
Construction Hints
Reset circuit - You can eliminate C-2 and replace it with a DS1813 reset IC. I've placed the required +5vdc hole between the holes used by C-2 for that purpose.   You could then cut the trace between P-2 and P-4 and have an additional pull-up resistor from RP-2 at P-2.
Here was my thinking in setting up the spare NAND gates.   First of all, be sure to cut the traces near P18 and P20 that lead to ground before using the spare gates!   If you take the output of the 8-IN NAND (pin 2 of IC6) and run it to the 1st inverter (P18) and the A7 line (P16) to the second (P20), then the output of the third (P22) would be an active low decoded output of $7F00 - $7F7F.   By jumpering up the 6522 as described above, it would appear at $7F80-$7FFF.   You can further eliminate the RP-1 and just put a single 22k resistor in pins 1 & 2 for the EEPROM WR enable and use the 8 open holes for D0-D7 access.   This provides D0-D7, A0-A6, MWR, MRD, and $7F00-$7F7F select for a daughter board.